1. Field of the Invention
The present invention relates to a sense amp circuit for a semiconductor device, and in particular to an improved sense amp circuit for a semiconductor device which can reduce current consumption when a power voltage is high, and which can improve an operation property of a sense amp when the power voltage is low, by adjusting a pull-up bias voltage and a pull-down bias voltage of the sense amp according to a magnitude of the power voltage.
2. Description of the Background Art
FIG. 1 is a structure diagram illustrating a conventional sense amp and a control circuit thereof, including a memory cell unit 10, a selecting driver unit 20 and a sense amp unit 30.
The memory cell unit 10 is composed of a plurality of memory cells. The sense amp unit 30 senses and amplifies the data from the memory cell unit 10 in a read operation, or senses and amplifies an input data in a write operation and stores it in the memory cell unit 10.
The selecting driver unit 20 generates first and second pull-up control signals SP1B and SP2B for sequentially supplying an external voltage EX_VDD and an internal voltage VDC to a pull-up bias node A of the sense amp according to a sense amp enable signal SAEN and an address decoding signal, and also generates a pull-down control signal SN1 for discharging a voltage of a pull-down bias node B of the sense amp to a ground voltage Vss.
FIG. 2 is a circuit diagram illustrating the selecting driver unit 20 of FIG. 1.
The selecting driver unit 20 receives the address decoding signal and the sense amp enable signal SAEN, and generates the first and second pull-up control signals SP1B and SP2B and the pull-down control signal SN1. The first pull-up control signal SP1B controls an operation of an NMOS transistor N3 supplying the external power voltage EX_VDD to the sense amp pull-up bias potential A in the sense amp operation, and the second pull-up control signal SP2B controls an operation of an NMOS transistor N4 supplying the internal power voltage VDC to the sense amp pull-up bias node A in the sense amp operation. In addition, the pull-down control signal SNl controls an operation of an NMOS transistor N5 discharging a voltage of the sense amp pull-down bias node B to the ground voltage Vss in the sense amp operation.
Here, the first pull-up control signal SP1B operates the NMOS transistor N3 in an initial operation of the sense amp, thereby supplying the external voltage EX_VDD to the pull-up bias node A of the sense amp. Accordingly, the sense amp is over-driven in its initial operation. At this time, the sense amp receives the external voltage EX_VDD, and rapidly pulls up the pull-up bias node A in a high power voltage VDD. Thereafter, the second pull-up control signal SP2B is enabled to turn on the NMOS transistor N4, thereby supplying the internal power voltage VDC to the pull-up bias node A. As a result, the sense amp is stably operated by the pull-up bias node A having the internal power voltage VDC.
However, in the conventional sense amp and the control circuit thereof, the external power voltage EX_VDD is supplied to the pull-up bias node A of the sense amp according to the first pull-up control signal SP1B in the initial operation of the sense amp. Here, the first pull-up control signal SP1B has a constant pulse width regardless of a magnitude of the power voltage VDD. When the power voltage VDD is high, a large current is unnecessarily supplied to the sense amp, which increases current consumption. In the case that the power voltage VDD is low, the current is not sufficiently supplied to the pull-up bias node A of the sense amp in a fixed pulse period, thereby deteriorating the operation of the sense amp.
Moreover, the pull-down bias node B of the sense amp pulls down the pull-down bias potential B according to one pull-down control signal SN1. As identical to the pull-up bias potential A, the pull-down bias node B does not sufficiently pull down the pull-down bias potential B in a low power voltage VDD.
Accordingly, it is an object of the present invention to provide a sense amp circuit for a semiconductor device which can reduce current consumption when a power voltage is high, and which can improve an operation property of a sense amp when the power voltage is low, by adjusting a pull-up bias voltage and a pull-down bias voltage of the sense amp according to a magnitude of the power voltage.
In order to achieve the above-described object of the invention, there is provided a sense amp circuit for a semiconductor device, including: a first pull-up driver for supplying an external power voltage to a pull-up bias node of the sense amp according to a first pull-up control signal; a second pull-up driver for supplying an internal power voltage to the pull-up bias node according to a second pull-up control signal; a first pull-down driver for discharging a voltage of a pull-down bias node of the sense amp into a ground voltage according to the first pull-down control signal; a second pull-down driver for discharging a voltage of the pull-down bias node into a ground voltage according to a second pull-down control signal; a voltage detector for generating a detecting signal by comparing a magnitude of the internal power voltage with a reference voltage according to a word line control signal before the sense amp operation; and a selecting driver for receiving the detecting signal, an address decoding signal and a sense amp enable signal, for generating the first pull-up control signal having a first pulse width in an initial operation of the sense amp, generating the second pull-up control signal, and generating the first pull-down control signal according to the sense amp enable signal when the internal power voltage is high according to the detecting signal, and for generating the first pull-up control signal having a second pulse width greater than the first pulse width in the initial operation of the sense amp, generating the second pull-up control signal, and generating the first and second pull-down control signals according to the sense amp enable signal when the internal power voltage is low.